This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits typically include wires (or other conductors) that are formed to transfer power and other electrical signals. Each wire may have a wire pitch that refers to a sum of a width and space of the wire. Standard cell (SC) placement and routing tools typically involve routing wires on predetermined pitches and at predetermined positions within various layers on integrated circuits. Power wires are typically placed in a repeating pattern across the design. In some cases, pre-placed obstructions in a floorplan of an integrated circuit design can leave areas of standard cell (SC) placement with no or inadequate power as these obstructions can block all access up to its top metal layer. The rectilinear nature of many floorplans can also interfere with the repeating pattern. Two traditional approaches to resolving this issue are inserting more power nets than required to meet IR drop requirements or restricting how the obstructions are placed to insure the standard cell (SC) placement areas between them receive an adequate amount of supply. The first approach blocks more resources for signal routing than necessary. The second approach can waste area or lead the an inefficient floorplan by moving the obstructions from their ideal positions. Both can negatively affect the power, performance, and area goals for the integrated circuit design. Therefore, there exists a need to improve integrated circuit designs to adequately supply power to more areas of a floorplan.